1. An open-drain gate is the CMOS counterpart of ________.
2. A TTL NAND gate with IIL(max) of –1.6 mA per input drives eight TTL inputs. How much current does the drive output sink?
3. The nominal value of the dc supply voltage for TTL and CMOS is ________.
4. Which logic family combines the advantages of CMOS and TTL?
5. Which equation is correct?
6. The active switching element used in all TTL circuits is the ________.
7. An open-collector output requires ________.
8. Most TTL logic used today is some form of ________.
9. A standard TTL circuit with a totem-pole output can sink, in the LOW state (IOL(max)), ________.
10. One output structure of a TTL gate is often referred to as a ________.
11. It is best not to leave unused TTL inputs unconnected (open) because of TTL's ________.
12. Which is not an output state for tristate logic?
13. TTL is alive and well, particularly in ________.
14. A TTL NAND gate with IIH(max) of 40 A per input drives ten TTL inputs. How much current does the drive output source?
15. A certain gate draws 1.8 A when its output is HIGH and 3.3 µA when its output is LOW. VCC is 5 V and the gate is operated on a 50% duty cycle. What is the average power dissipation (PD)?
16. PMOS and NMOS circuits are used largely in ________.
17. If ICCH is specified as 1.1 mA when VCC is 5 V and if the gate is in a static (noncharging) HIGH output state, the power dissipation (PD) of the gate is ________.
18. Which is not a precaution for handling CMOS?
19. Which factor does not affect CMOS loading?
20. Which is not part of emitter-coupled logic (ECL)?
21. The speed-power product provides a basis for the comparison of logic circuits when power dissipation and propagation delay are important considerations in the selection of the type of logic to be used.
22. ECL IC technology is faster than TTL technology.
23. CMOS is a more dominant IC technology than TTL.
24. Unused TTL inputs should be tied LOW.
25. The greater the propagation delay, the higher the maximum frequency.