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You Are On Multi Choice Question Bank SET 949

47451. Create Co-operators before creating Co-operatives pointed out by-----------committee.

47452. The MOD-10 counter is also referred to as a ________ counter.

47453. Co-operative Principles were formulated by----------conference

47454. In general, when using a scope to troubleshoot digital systems the instrument should be triggered by ________.

47455. World food day on:

47456. ________ counters are often used whenever pulses are to be counted and the results displayed in decimal.

47457. Co-operation has failed but it most succeed expressed by:

47458. The technique used by one-shots to respond to an edge rather than a level is called ________.

47459. Se43 of the IPC deals with

47460. A J-K flip-flop is reset and must stay reset after the clock pulse. This transition requires that ________.

47461. Occupies an important position in the democratic setup of the society

47462. ________ is the modulus of the counter shown below.

47463. Sec-provides that a society are exempted from stamp duty.

47464. The ________ counter in the Altera library has controls that allow it to count up or down, and perform synchronous parallel load and asynchronous cascading.

47465. From-statement the Society prepared the fiani accounts.

47466. A BCD counter has ________ states.

47467. Subjudice means:

47468. The decimal equivalent of the largest number that can be stored in a 4-bit binary counter is ________.

47469. The minimum number of flip-flops that can be used to construct a modulus-5 counter is ________.

47470. The duty cycle of the most significant bit from a 4-bit (0–9) BCD counter is ________.

47471. Shift-register counters use ________, which means that the output of the last FF in the register is connected back to the first FF in some way.

47472. The counter circuit and associated waveforms shown below are for a(n) ________ counter, and the correct output waveform for QB is shown by waveform ________.

47473. Asynchronous counters are often called ________ counters.

47474. The given circuit is a(n) ________.

47475. How many flip-flops are required to make a MOD-32 binary counter?

47476. Using four cascaded counters with a total of 16 bits, how many states must be deleted to achieve a modulus of 50,000?

47477. A MOD-16 ripple counter is holding the count 10012. What will the count be after 31 clock pulses?

47478. The terminal count of a modulus-11 binary counter is ________.

47479. List which pins need to be connected together on a 7493 to make a MOD-12 counter.

47480. How can a digital one-shot be implemented using HDL?

47481. Which of the figures (a to d) is the DeMorgan equivalent of Figure (e)?

47482. means the document itself produced for the inspection of the Court.

47483. In VHDL, the mode of a port does not define:

47484. Which of the following equations would accurately describe a 4-input OR gate when A = 1, B = 1, C = 0, and D = 0?

47485. Which of the examples below expresses the distributive law?

47486. Which of the examples below expresses the associative law of addition:

47487. How are the statements between BEGIN and END not evaluated in VHDL?

47488. Which logic gate does this truth table describe?

47489. For a 3-input NAND gate, with the input waveforms as shown below, which output waveform is correct?

47490. Which of the figures given below represents a NAND gate?

47491. Which timing diagram shown below is correct for an inverter?

47492. A NOR gate with one HIGH input and one LOW input:

47493. A NAND gate has:

47494. Which of the figures given below represents an OR gate?

47495. The method of proportional representation is adopted in the election of?

47496. The logic gate that will have HIGH or "1" at its output when any one of its inputs is HIGH is a(n):

47497. Which of the symbols shown below represents an AND gate?

47498. For a three-input AND gate, with the input waveforms as shown below, which output waveform is correct?

47499. An OR gate with inverted inputs functions as:

47500. The special software application that translates from HDL into a grid of 1's and 0's, which can be loaded into a PLD, is called a:

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