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digital electronics logic gates
1. A clock signal with a period of 1 s is applied to the input of an enable gate. The output must contain six pulses. How long must the enable pulse be active?
(A): Enable must be active for 0 s.
(B): Enable must be active for 12 s.
(C): Enable must be active for 3 s.
(D): Enable must be active for 6 s.
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