Question Set

1. In a 74164 8-bit shift register, in order for the parallel data output to be synchronously loaded on the negative clock edge, the parallel enable input is LOW.



Ask Your Doubts Here

Type in
(Press Ctrl+g to toggle between English and the chosen language)

Comments

Show Similar Question And Answers
QA->പ്രകാശത്തിൻറെ Red Shift, Blue Shift എന്നീ പ്രതിഭാസങ്ങൾക്ക് കാരണം....
QA->A pendulum clock is set to give correct time at the sea level. This clock is moved to a hill station at an altitude of 2500m above the sea level. In order to keep correct time on the hill station, the length of the pendulum?....
QA->Under which Five - year plan did agriculture register a negative growth?....
QA->Paper in which cellulose fibers are parallel the shortest edge of the sheet ?....
QA->What function displays row data in a column or column data in a row?....
MCQ->In a 74164 8-bit shift register, in order for the parallel data output to be synchronously loaded on the negative clock edge, the parallel enable input is LOW.....
MCQ->Read the following statements as regards register pairs in microprocessor 8085B represents B, C pair with B as high order register and C as low order register.D represents D, E pair with D as high order register and E as low order register.H represents H, L pair with H as high order register and L as low order register. Which of the above statements are correct?....
MCQ->The 54/74164 chip is an 8-bit serial-input-parallel-output shift register. The clock is 1 MHz. The time needed to shift a 8-bit binary number into the chip is....
MCQ->A bidirectional 4-bit shift register is storing the nibble 1110. Its input is LOW. The nibble 0111 is waiting to be entered on the serial data-input line. After two clock pulses, the shift register is storing ________.....
MCQ->Consider the following statements: For a master-slave J-K flip-flop, the toggle frequency is the maximum clock frequency at which the flip-flop will toggle reliably.the data input must precede the clock triggering edge transition time by time minimum time.the data input must remain fixed for a given time after, the clock triggering edge transition time for reliable operation.propagation delay time is equal to the rise time and fall time of the data. Which of the above statements is/are correct?....
Terms And Service:We do not guarantee the accuracy of available data ..We Provide Information On Public Data.. Please consult an expert before using this data for commercial or personal use | Powered By:Omega Web Solutions
© 2002-2017 Omega Education PVT LTD...Privacy | Terms And Conditions
Question ANSWER With Solution