Question Set

1. What is a disadvantage of CMOS in place of TTL?





Ask Your Doubts Here

Type in
(Press Ctrl+g to toggle between English and the chosen language)

Comments

Show Similar Question And Answers
QA->CMOS - പൂര്‍ണ്ണ രൂപം?....
QA->What is full form CMOS?....
QA->The latitude of a place expresses its angular position relative to the place of which point?....
QA->The latitude of a place is the same as which place?....
QA->The latitude of a place expresses its angular position relative to the which place?....
MCQ->Assertion (A): Even if TTL gates and CMOS gates used in a realization have the same power supply of + 5 V, suitable circuit is needed to interconnect themReason (R): VOH, VOL, VIH and VIL of a TTL gave are respectively 2.4, 0.4, 2 and 0.8 V respectively. If supply voltage is + 5 V. VIL and VIH for CMOS gate for the supply voltage of + 5 V are 1.5 V and 3.5 V respectively.

....
MCQ->What is a disadvantage of CMOS in place of TTL?....
MCQ->Due to the extremely low power requirements of CMOS logic circuits, any number of CMOS and TTL gates can be interconnected.....
MCQ->The problem of the VOH(min) of a TTL IC being too low to drive a CMOS circuit and meet the CMOS requirement of VIH(min) is usually easily overcome by:....
MCQ->One advantage TTL has over CMOS is that TTL is ________.....
Terms And Service:We do not guarantee the accuracy of available data ..We Provide Information On Public Data.. Please consult an expert before using this data for commercial or personal use | Powered By:Omega Web Solutions
© 2002-2017 Omega Education PVT LTD...Privacy | Terms And Conditions
Question ANSWER With Solution