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electronics and communication engineering microprocessors
1. In 8085
(A): RST 5.5 is low level sensitive interrupt but RST 5.5 is high level-sensitive interrupt
(B): RST 5.5 is low level sensitive interrupt but RST 6.5 is high level sensitive interrupt
(C): RST 6.5 and RST 5.5 are high level sensitive interrupts
(D): RST 6.5 and RST 5.5 are low level sensitive interrupts
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MCQ->Assertion (A): In 8085 SP and PC are 8 bit each.Reason (R): 8085 is an 8 bit microprocessor.....
MCQ->Assertion (A): Microprocessor 8085 can address 65536 memory locations.Reason (R): Microprocessor 8085 has 16 address lines.....
MCQ->Assertion (A): In 8085, the zero flag is set when ALU operation results in 0. If the result is not 0, this flag is reset.Reason (R): In 8085 the S flag is set when the contents of accumulator become negative during execution of an instruction.....
MCQ->Assertion (A): In microprocessor 8085 instruction LXIB, 90 FF H means register B and C are loaded with upper and lower bytes to get B = 90 H and C = FFH.Reason (R): In 8085 the stack pointer indicates which memory location is to accessed.....
MCQ->Assertion (A): Microprocessor 8085 has facility of interrupt control.Reason (R): TRAP, RST 7.5, RST 6.5, RST 5.5 and 1NTR are interrupt signals in 8085.....
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