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electronics and communication engineering digital electronics
1. A 4 bit synchronous counter uses flip flops with a delay time of 15 ns each. The time required for change of state is
(A): 15 ns
(B): 30 ns
(C): 45 ns
(D): 60 ns
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By: guest on 01 Jun 2017 11.53 pm
In a synchronous counter clock input is applied to all flip flops simultaneously. Hence total delay time is 15 ns.
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