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1. Refer to the NAND and NOR latches shown in the figure. The inputs (P1, P2) for both the latches are first made (0, 1) and then, after a few seconds, made (1, 1). The corresponding stable outputs (Q1, Q2) are
(A): NAND: first (0, 1) then (0, 1) NOR: first (1, 0) then (0, 0)
(B): NAND: first (1, 0) then (1, 0) NOR: first (1, 0) then (0, 0)
(C): NAND: first (1, 0) then (1, 0) NOR: first (1, 0) then (1, 0)
(D): NAND: first (1, 0) then (1, 1) NOR: first (0, 1) then (0, 1)
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