48001. The exclusive-OR provides a LOW input if one input or the other input is HIGH.
48002. The exclusive-OR is written in a Boolean equation as a plus sign with a circle around it.
48003. Parity generator and checker circuits are available in single IC packages.
48004. The Ex-NOR is sometimes called the equality gate.
48005. A parity checker is constructed in the same way as a parity generator, except that in a 4-bit system there must be five inputs, and the output is used as the error indicator.
48006. In a parity generator circuit, an error is signaled on an error indicator.
48007. Select the statement that best describes the parity method of error detection:
48008. A logic circuit that provides a HIGH output for both inputs HIGH or both inputs LOW is a(n):
48009. A logic circuit that provides a HIGH output if one input or the other input, but not both, is HIGH, is a(n):
48010. Identify the type of gate below from the equation
48011. How is odd parity generated differently from even parity?
48012. Which is not an Altera primitive port identifier?
48013. The timing network that sets the output frequency of a 555 astable circuit contains ________.
48014. What is the difference between the enable input of the 7475 and the clock input of the 7474?
48015. The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is HIGH is called ________.
48016. What is another name for a one-shot?
48017. On a master-slave flip-flop, when is the master enabled?
48018. One example of the use of an S-R flip-flop is as a(n):
48019. What is the difference between the 7476 and the 74LS76?
48020. Which of the following is correct for a gated D flip-flop?
48021. With regard to a D latch, ________.
48022. How can the cross-coupled NAND flip-flop be made to have active-HIGH S-R inputs?
48023. When is a flip-flop said to be transparent?
48024. Four positive edge-triggered D flip-flops are used to store a 4-bit binary number as shown below. Determine if the circuit is functioning properly, and if not, what might be wrong.
48025. A 555 operating as a monostable multivibrator has an R1 of 1 M. Determine C1 for a pulse width of 2 s.
48026. Master-slave J-K flip-flops are called pulse-triggered or level-triggered devices because input data is read during the entire time the clock pulse is at a LOW level.
48027. Which of the following is correct for a D latch?
48028. A J-K flip-flop is in a "no change" condition when ________.
48029. A correct output is achieved from a master-slave J-K flip-flop only if its inputs are stable while the:
48030. Which of the following describes the operation of a positive edge-triggered D flip-flop?
48031. What does the triangle on the clock input of a J-K flip-flop mean?
48032. A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________.
48033. The toggle condition in a master-slave J-K flip-flop means that Q and will switch to their ________ state(s) at the ________.
48034. An RC circuit used in a nonretriggerable 74121 one-shot has an REXT of 49 k and a CEXT of 0.2 F. The pulse width (tW) is approximately ________.
48035. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________.
48036. What is the hold condition of a flip-flop?
48037. If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be ________.
48038. In VHDL, how many inputs will a primitive JK flip-flop have?
48039. A 555 operating as a monostable multivibrator has a C1 = 0.01 F. Determine R1 for a pulse width of 2 ms.
48040. A D flip-flop utilizing a PGT clock is in the CLEAR state. Which of the following input actions will cause it to change states?
48041. The symbols on this flip-flop device indicate ________.
48042. In a 555 timer, three 5 k resistors provide a trigger level of ________.
48043. Does the cross-coupled NOR flip-flop have active-HIGH or active-LOW set and reset inputs?
48044. The circuit that is primarily responsible for certain flip-flops to be designated as edge-triggered is the:
48045. With four J-K flip-flops wired as an asynchronous counter, the first output change of divider #4 indicates a count of how many input clock pulses?
48046. What is the significance of the J and K terminals on the J-K flip-flop?
48047. Why are the S and R inputs of a gated flip-flop said to be synchronous?
48048. Gated S-R flip-flops are called asynchronous because the output responds immediately to input changes.
48049. Which of the following is not generally associated with flip-flops?
48050. An RC circuit used in a 74122 retriggerable one-shot has an REXT of 100 k and a CEXT of 0.005 F. The pulse width is ________.