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You Are On Multi Choice Question Bank SET 986

49301. Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.)





49302. A serial in/parallel out, 4-bit shift register initially contains all 1s. The data nibble 0111 is waiting to enter. After four clock pulses, the register contains ________.





49303. With a 200 kHz clock frequency, eight bits can be serially entered into a shift register in ________.





49304. An 8-bit serial in/serial out shift register is used with a clock frequency of 2 MHz to achieve a time delay (td) of ________.





49305. A sequence of equally spaced timing pulses may be easily generated by which type of counter circuit?





49306. The bit sequence 10011100 is serially entered (right-most bit first) into an 8-bit parallel out shift register that is initially clear. What are the Q outputs after four clock pulses?





49307. If an 8-bit ring counter has an initial state 10111110, what is the state after the fourth clock pulse?





49308. How would a latch circuit be used in a microprocessor system?




49309. A 4-bit shift register that receives 4 bits of parallel data will shift to the ________ by ________ position(s) for each clock pulse.





49310. How many clock pulses will be required to completely load serially a 5-bit shift register?





49311. How is a strobe signal used when serially loading a shift register?





49312. An 8-bit serial in/serial out shift register is used with a clock frequency of 150 kHz. What is the time delay between the serial input and the Q3 output?





49313. What are the three output conditions of a three-state buffer?





49314. The primary purpose of a three-state buffer is usually:





49315. What is the difference between a ring shift counter and a Johnson shift counter?





49316. What is a recirculating register?




49317. When is it important to use a three-state buffer?





49318. A bidirectional 4-bit shift register is storing the nibble 1110. Its input is LOW. The nibble 0111 is waiting to be entered on the serial data-input line. After two clock pulses, the shift register is storing ________.





49319. In a parallel in/parallel out shift register, D0 = 1, D1 = 1, D2 = 1, and D3 = 0. After three clock pulses, the data outputs are ________.





49320. The group of bits 10110111 is serially shifted (right-most bit first) into an 8-bit parallel output shift register with an initial state 11110000. After two clock pulses, the register contains ________.





49321. By adding recirculating lines to a 4-bit parallel-in, serial-out shift register, it becomes a ________, ________, and ________-out register.





49322. What type of register would have a complete binary number shifted in one bit at a time and have all the stored bits shifted out one at a time?





49323. When an 8-bit serial in/serial out shift register is used for a 20 s time delay, the clock frequency is ________.





49324. Ring shift and Johnson counters are:





49325. What is the difference between a shift-right register and a shift-left register?



49326. What is a transceiver circuit?




49327. A 74HC195 4-bit parallel access shift register can be used for ________.





49328. Which type of device may be used to interface a parallel data format with external equipment's serial format?





49329. What is the function of a buffer circuit?





49330. What is the preset condition for a ring shift counter?





49331. Which is not characteristic of a shift register?





49332. To keep output data accurate, 4-bit series-in, parallel-out shift registers employ a ________.





49333. With a 50 kHz clock frequency, six bits can be serially entered into a shift register in ________.





49334. Another way to connect devices to a shared data bus is to use a ________.





49335. To serially shift a nibble (four bits) of data into a shift register, there must be ________.





49336. Computers operate on data internally in a ________ format.





49337. In a 4-bit Johnson counter sequence there are a total of how many states, or bit patterns?





49338. If a 10-bit ring counter has an initial state 1101000000, what is the state after the second clock pulse?





49339. How much storage capacity does each stage in a shift register represent?





49340. When the output of a tristate shift register is disabled, the output level is placed in a:





49341. One of the stages in a register consists of a latch.



49342. There are several ways to construct a stepper motor to achieve digitally controlled stepping action. One possibility is to construct four stator coils set up as four pole pairs, each 45° apart and using three ferromagnetic pairs spaced 60° apart.



49343. A parallel load operation is asynchronous, so it is not dependent on the clock.



49344. A ferromagnetic material is one that forms a resistance to magnetic fields.



49345. A counter has a specified sequence of states, but a shift register does not.



49346. In a 74164 8-bit shift register, in order for the parallel data output to be synchronously loaded on the negative clock edge, the parallel enable input is LOW.



49347. Practically every possible load, shift, and conversion operation is available in a shift register IC.



49348. Using separate serial inputs for shifting left or shifting right is a major difference between the 74194 and other shift registers.



49349. Parallel load means to load all flip-flops at the same time.



49350. The ring and Johnson shift counters are uncommon circuits that are similar to synchronous counters.



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