76. How many different states does a 2-bit asynchronous counter have?
77. A 12 MHz clock frequency is applied to a cascaded counter containing a modulus-5 counter, a modulus-8 counter, and a modulus-10 counter. The lowest output frequency possible is ________.
78. Bidirectional shift registers can shift data either right or left.
79. In many cases, counters must be strobed in order to eliminate glitches.
80. A state diagram is a table of states.
81. A ripple counter is an asynchronous counter.
82. The MOD number of a Johnson counter will always be equal to one-half the number of flip-flops in the counter.
83. To cascade is to connect in parallel.
84. Cascade means to connect the Q output of one flip-flop to the clock input of the next.
85. In a synchronous counter, each state is clocked by the same pulse.
86. Basic counters can be cascaded in parallel to increase the number of data bits that the counter can handle.
87. In a 74192 BCD decade up-/down-counter, the terminal count up and the terminal count down are active-LOW.
88. Dependency notation is no longer used.
89. A parallel in/serial out shift register enters all data bits simultaneously and transfers them out one bit at a time.
90. Generally speaking, the synchronous counter requires more circuitry than an asynchronous counter.
91. Another term used to describe up/down counters is bidirectional.
92. When implementing a complete system application using IC counter chips, output devices such as LED indicators must be configured to operate from the counter outputs.
93. One characteristic of a ring counter is that the modulus is equal to the number of flip-flops in the register and, consequently, there are never any unused or invalid states.
94. In a full-featured counter in HDL, the concept of rolling over simply means the count sequence has reached its limit and must start over at the beginning of the sequence.
95. The 7447 has a 4-bit BCD input, seven individual active-LOW outputs, and a ripple blanking input and output.
96. All decade counters are BCD counters.
97. Shift register counters use logic functions to reset the registers when the desired count is reached.
98. Three cascaded modulus-10 counters have an overall modulus of 1000.
99. A reliable method for eliminating decoder spikes is to use strobing.
100. An asynchronous counter differs from a synchronous counter in the method of clocking.