151. A J-K flip-flop is reset and must stay reset after the clock pulse. This transition requires that ________.
152. ________ is the modulus of the counter shown below.
153. The ________ counter in the Altera library has controls that allow it to count up or down, and perform synchronous parallel load and asynchronous cascading.
154. A BCD counter has ________ states.
155. The decimal equivalent of the largest number that can be stored in a 4-bit binary counter is ________.
156. The minimum number of flip-flops that can be used to construct a modulus-5 counter is ________.
157. The duty cycle of the most significant bit from a 4-bit (0–9) BCD counter is ________.
158. Shift-register counters use ________, which means that the output of the last FF in the register is connected back to the first FF in some way.
159. The counter circuit and associated waveforms shown below are for a(n) ________ counter, and the correct output waveform for QB is shown by waveform ________.
160. Asynchronous counters are often called ________ counters.
161. The given circuit is a(n) ________.
162. How many flip-flops are required to make a MOD-32 binary counter?
163. Using four cascaded counters with a total of 16 bits, how many states must be deleted to achieve a modulus of 50,000?
164. A MOD-16 ripple counter is holding the count 10012. What will the count be after 31 clock pulses?
165. The terminal count of a modulus-11 binary counter is ________.
166. List which pins need to be connected together on a 7493 to make a MOD-12 counter.
167. How can a digital one-shot be implemented using HDL?