Toggle navigation
Home
KPSC Previous Question Papers
Article Category
kerala psc
upsc
General
Popular Pages
Multiple Choice Question in aptitude-area
Multiple Choice Question in non-verbal-reasoning-grouping-of-images
Multiple Choice Question in aptitude-compound-interest
Multiple Choice Question in engineering-mechanics-kinetics-of-a-particle-impulse-and-momentum
Multiple Choice Question in database-database-redesign
Multiple Choice Question in 035/2016
Question Answer in malayalam-kerala-psc-questions
Multiple Choice Question in malayalam-kerala-psc-questions
Multiple Choice Question in current-affairs-2017-03-05
Question Answer in KERALA PSC
Multiple Choice Question in KERALA PSC
Multiple Choice Question in electronic-devices-bipolar-junction-transistors
Question Answer Bank
Multiple Choice Question Bank
Question Answer Category
Multiple Choice Question Category
Home
->
Multiple Choice Questions
Question Set
electronics and communication engineering digital electronics
1. ECL is a saturating logic.
(A): False
(B): True
Previous Question
Show Answer
Next Question
Add Tags
Report Error
Show Marks
Ask Your Doubts Here
Type in
(Press Ctrl+g to toggle between English and the chosen language)
Post reply
Comments
By: guest on 01 Jun 2017 11.53 pm
It is a non-saturating logic. Hence highest speed of operation.
Show Similar Question And Answers
QA->Arithmetic Logic പ്രവർത്തനങ്ങൾക്കായുള്ള കംപ്യൂട്ടറിലെ Local Storage Area ഏത്? ....
QA->Arithmetic and Logic Unit ന്റെ ധർമം എന്ത്? ....
QA->The function of Arithmetic and Logic Unit (ALU) is?....
QA->Arithmetic Logic പ്രവർത്തനങ്ങൾക്കായുള്ള കമ്പ്യുട്ടറി ലെ Iocal storage area?....
MCQ->ECL is a saturating logic.....
MCQ->Assertion (A): ECL gate has very high speed of operation.Reason (R): Transistors in ECL do not go into saturation region.....
MCQ->Assertion (A): ECL is fast as compared to TTL.Reason (R): ECL dissipates less power than TTL.....
MCQ->Assertion (A): The propagation delay in ECL is minimum Reason (R): Transistors used in ECL switch between active and cutoff regions.....
MCQ->A major drawback in using ECL logic circuits in conjunction with TTL and MOS circuits is its negative supply voltages and logic levels.....
×
×
Type The Issue
×
Your Marks
Terms And Service:We do not guarantee the accuracy of available data ..We Provide Information On Public Data.. Please consult an expert before using this data for commercial or personal use | Powered By:Omega Web Solutions
© 2002-2017 Omega Education PVT LTD...
Privacy
|
Terms And Conditions
Question ANSWER With Solution