101. The terminal count of a typical modulus-10 binary counter is 1010.
102. A J-K flip-flop excitation table lists the present state, the next state, and the J and K levels required to produce each transition.
103. The concept of a counter to implement a digital one-shot using HDL is not used.
104. The modulus of a counter is the actual number of states in its sequence.
105. All flip-flops in an asynchronous counter change states at the same time.
106. A glitch is a short pulse resulting in an undesired result in a digital circuit.
107. Asynchronous counters are known as modulus counters.
108. In VHDL, when we want to remember a value it must be stored in a VARIABLE.
109. In a seven-segment LED display, the BCD must be decoded into a format that can be used to drive the decimal numeric display.
110. Parallel in/parallel out registers have parallel input and output busses.
111. Once an up/down counter begins its count sequence, it cannot be reversed.
112. Shift registers are used to store and transfer data.
113. An effective time delay device can be constructed by using the propagation delay characteristic of parallel shift registers.
114. The term synchronous refers to events that do not occur at the same time.
115. Synchronous binary counters can only be used for the application of timing of digital systems.
116. The terminal marked A on the CTR block in the given figure is the SET terminal.
117. The term synchronous, as applied to counter operations, means that the counter is clocked such that each flip-flop in the counter is triggered at the same time.
118. Counters are generally decoded in order to determine their count state.
119. Phototransistors have varying resistance from collector to emitter, depending on how much light strikes them.
120. Most sequential circuits contain a combinational logic section and a memory section.
121. A serial in/serial out shift register transfers data from one line of a parallel bus to another line one bit at a time.
122. The serial in/parallel out shift register transfers data from one parallel data bus to another parallel data bus one bit at a time across a single line.
123. To design a divide-by-200 counter using synchronous counters, two 4-bit counters could be cascaded together to form an 8-bit counter.
124. When a J-K flip-flop is used in a circuit, we only have to consider the level at J and K at the active clock edge to know the states of the outputs.
125. A reliable method for eliminating decoder spikes is the technique called ________.