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You Are On Multi Choice Question Bank SET 944

47201. Machine language is independent of the type of microprocessor in a computer system.



47202. The PCI bus is a good example of an external bus for personal computers.



47203. The Power PC can effectively execute up to ten instructions per clock cycle.



47204. Polling is the process of pausing the normal sequence of instructions to cause the processor to execute a separate set of I/O instructions instead.



47205. The AND, OR, and TEST instructions are all part of which type of instruction?





47206. A mini-program that can be used repeatedly, but is programmed only once is called a(n) ________.





47207. Contiguous sequences of bytes or words are called ________.





47208. An interrupt method that requires the CPU to test each peripheral device in sequence is called ________.





47209. An example of a unidirectional bus in a microcomputer system is the ________.





47210. The ADD, CMP, and MUL instructions are all part of which type of instruction?





47211. Instructions that allow direct control of the processor's flags are called ________ instructions.





47212. The MOV, PUSH, and POP instructions are all part of which type of instruction?





47213. The JNZ, JA, and LOOP instructions are all part of which type of instruction?





47214. During a memory read operation, the CPU fetches ________.





47215. Which of the following is not a basic element within the microprocessor?





47216. Which method bypasses the CPU for certain types of data transfer?





47217. Which of the following is not an enhancement to the Pentium that was unavailable in the 8086/8088?





47218. Which bus is bidirectional?





47219. DMA is particularly suited for data transfer between the ________.





47220. Integrated-circuit counter chips are used in numerous applications including:





47221. Synchronous construction reduces the delay time of a counter to the delay of:





47222. Synchronous counters eliminate the delay problems encountered with asynchronous counters because the:





47223. What is the difference between combinational logic and sequential logic?




47224. What is the difference between a 7490 and a 7492?





47225. What type of register is shown below?





47226. When two counters are cascaded, the overall MOD number is equal to the ________ of their individual MOD numbers.





47227. A MOD-12 and a MOD-10 counter are cascaded. Determine the output frequency if the input clock frequency is 60 MHz.





47228. Which segments of a seven-segment display would be required to be active to display the decimal digit 2?





47229. How many AND gates would be required to completely decode ALL the states of a MOD-64 counter, and how many inputs must each AND gate have?





47230. What decimal value is required to produce an output at "X" ?





47231. A BCD counter is a ________.





47232. The circuit given below has no output on Q1 when examined with an oscilloscope. All J-K inputs are HIGH, the CLK signal is present, and the Q0 is toggling. The C input of FF1 is a constant LOW. What could be causing the problem?





47233. How many flip-flops are required to construct a decade counter?





47234. The terminal count of a typical modulus-10 binary counter is ________.





47235. A seven-segment, common-anode LED display is designed for:





47236. To operate correctly, starting a ring counter requires:





47237. The process of designing a synchronous counter that will count in a nonbinary manner is primarily based on:





47238. Select the response that best describes the use of the Master Reset on typical 4-bit binary counters.





47239. For a multistage counter to be truly synchronous, the ________ of each stage must be connected to ________.





47240. Which of the following is an invalid output state for an 8421 BCD counter?





47241. How many different states does a 3-bit asynchronous counter have?





47242. A 5-bit asynchronous binary counter is made up of five flip-flops, each with a 12 ns propagation delay. The total propagation delay (tp(tot)) is ________.





47243. A four-channel scope is used to check the counter in the figure given below. Are the displayed waveforms correct?



47244. Which of the following procedures could be used to check the parallel loading feature of a counter?





47245. One of the major drawbacks to the use of asynchronous counters is:





47246. Once an up-/down-counter begins its count sequence, it cannot be reversed.



47247. Three cascaded modulus-5 counters have an overall modulus of ________.





47248. An asynchronous 4-bit binary down counter changes from count 2 to count 3. How many transitional states are required?





47249. The final output of a modulus-8 counter occurs one time for every ________.





47250. A 4-bit up/down binary counter is in the DOWN mode and in the 1100 state. To what state does the counter go on the next clock pulse?





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