47601. What is the correct output of the adder in the given figure, with the outputs in the order:

47602. The management of joint Stock Company is:

47603. The BCD addition of 910 and 710 will give initial code groups of 1001 + 0111. Addition of these groups generates a carry to the next higher position. The correct solution to this problem would be to:

47604. Subtract the following binary numbers.
0101 1000 1010 0011 1101 1110 –0010 0011 –0011 1000 –0101 0111

47605. Why is a fast-look-ahead carry circuit used in the 7483 4-bit full-adder?

47606. Find the 2's complement of –1101102.

47607. What logic function is the sum output of a half-adder?

47608. The binary adder circuit is designed to add ________ binary numbers at the same time.

47609. An ALU is a multipurpose device capable of providing several different logic operations.

47610. BCD arithmetic is performed using base 10 numbers.

47611. A full adder has a carry-in.

47612. Hexadecimal is a base 4 numbering system.

47613. The solution to the binary problem 00110110 – 00011111 is 00011000.

47614. A binary sum is made up of only 1s and 0s.

47615. Overflow indicators in ALU circuits indicate when add or subtract operations produce results that are too large to fit into four bits.

47616. The inputs of a full adder are labeled A1, B1, and Cin.

47617. Larger number capacities may be obtained from 2-bit adders by paralleling them.

47618. If [A] = 10 and [B] = 01, then [A] + [B] = [ ].

47619. 111010002 is the 2's-complement representation of –24.

47620. The look-ahead-carry adder is slower than the ripple-carry adder because it requires additional logic circuits.

47621. The solution to the binary problem 1011 × 0110 is 01100110.

47622. The solution to the BCD problem 0101 + 0100 is 00001001BCD.

47623. A macrofunction is a self-contained description of a logic circuit with all of its inputs, outputs, and operational characteristics defined.

47624. A half-adder circuit would normally be used each time a carry input is required in an adder circuit.

47625. The binary subtraction 0 – 1 = is
difference = 1
borrow = 0

47626. A sign bit of "1" in the difference of a 2's-complement subtraction problem indicates the magnitude is negative and in true binary form.

47627. Constants must be included in a package.

47628. 10011100 in two's-complement notation has a decimal value of –100.

47629. There are four possible combinations for subtracting two binary numbers.

47630. It is not necessary to have the same number of bits when adding or subtracting signed binary numbers in the 2's-complement system.

47631. Full adder results are typically stored in registers.

47632. The representation of –110 in eight-bit two's-complement notation is 11110111.

47633. Binary division and decimal division use the same procedure.

47634. When the 2's-complement system is used, the number to be subtracted is changed to its 2's complement and then added to the minuend.

47635. Full adders can add two numbers and need not have a carry input or a carry output.

47636. The VHDL compiler requires libraries to be specified at the beginning of the code if components from those libraries are being used.

47637. The carry-out of a binary adder is identified using the summation symbol, sigma.

47638. The 74LS382 ALU is a 24-pin arithmetic/logic unit.

47639. The two's-complement method is used in computer systems that perform arithmetic.

47640. Digital computers use an easier method to subtract binary numbers, called one's complement.

47641. Binary multiplication is like decimal multiplication except you deal only with 1s and 0s.

47642. The solution to the binary problem 1011 – 0111 is 1000.

47643. A 74HC283 can be used to implement a 4-bit full adder.

47644. The range of negative numbers when using an eight-bit two's-complement system is –1 to –128.

47645. If no bits are designated inside square braces, [ ], it means the variable is the null set.

47646. This logic gate is used to produce an arithmetic sum XOR.

47647. The solution to the binary problem 0101 + 1111 is 10100.

47648. ALU circuits cannot be cascaded to perform functions on more than four bits.

47649. In VHDL, the architecture declaration always begins with the ________ of variable signals or components that will be used in the concurrent description between BEGIN and END.

47650. When decimal numbers with several digits are to be added together using BCD adders ________.