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You Are On Multi Choice Question Bank SET 958

47901. In the keypad application, what does the data signal define?





47902. What does the ring counter in the HDL keypad application do when a key is pressed?





47903. In the digital clock project, the purpose of the frequency prescaler is to:





47904. Which is not a step that should be followed in project management?





47905. In the keypad application, what does the preset state of the ring counter define?





47906. In an HDL stepper motor design, why is there more than one mode?





47907. Which is not a major block of an HDL frequency counter?





47908. In a full-step sequence involving two flip-flops driving four coils of a stepper motor, how far will the stepper motor step?





47909. Which is not a step used to define the scope of an HDL project?





47910. In the digital clock project, what is the frequency of the MOD-6 counter in the minutes section?





47911. Why should a real hardware functional test be performed on the HDL stepper motor design?





47912. What does the major block of an HDL code emulation of a keypad include?





47913. The accuracy of the frequency counter depends on the:





47914. In the frequency counter, if the clock generator produces a 100 kHz system clock signal, how many decade counters are required to measure 1 Hz?





47915. What must a stepper motor HDL application include?





47916. Which is not a step in strategic planning for HDL development?





47917. In the frequency counter, when is the new count stored in the display register?





47918. What are two ways to remember the current state of a counter in VHDL?





47919. In the digital clock project, what type of counter is used to count to 59 seconds?





47920. In the keypad application, when all columns are HIGH, the ring counter is enabled and counting, and dav is LOW, what is the status of the d outputs?





47921. In the frequency counter, what is the function of the Schmitt trigger circuit?





47922. List three basic blocks in the digital clock project.





47923. When designing an HDL digital system, which is the worst mistake one can make?





47924. In the keypad application, just after the 4 ms mark the simulation imitates the release of the key by changing the column value back to F hex, which causes the d output to go into its Hi-Z state. On the next rising clock edge, what happens to dav?





47925. For the frequency counter, which is not a control signal from the control and timing block?





47926. Top-down design means that we start at the highest level of the hierarchy, or that the entire project is considered to exist in a closed dark box with inputs and outputs.



47927. The frequency counter measures frequency by enabling a counter to count the number of pulses of the incoming waveform during a precisely specified period of time called the sampling time.



47928. In the digital clock project, frequency prescaling is used to take a 1 pps input and transform it into a 60 pps timing signal.



47929. The half-step sequence of a stepper motor is created by inserting a start with only one coil energized between full steps.



47930. One of the first steps in any HDL project is to define its scope by knowing the nature of all the signals that are interconnected to pieces of the project.



47931. In HDL, one of the strategies used in strategic planning is to find a way to test each piece of the project.



47932. A very critical dimension in project management is the time your boss will give you to complete the HDL project.



47933. In the keypad HDL encoder, the data signal is used to combine the row and column encoder data to make a 4-bit value representing the key that was pressed.



47934. One CASE construct inside another CASE construct is called a do-loop.



47935. A frequency counter is a circuit that can measure and display the frequency of a signal.



47936. In the digital clock project, a MOD-60 BCD counter is made from a MOD-10 counter cascaded to a MOD-6 BCD counter.



47937. The full-step sequence always has two coils of the stepper motor energized in any state of the sequence and typically causes 30° of shaft rotation per step.



47938. The direct drive mode of a stepper motor allows for less control by the operator.



47939. In the frequency counter, a pulse shaper block is needed to ensure that the unknown signal, whose frequency is to be measured, will be compatible with the clock input for the counter block.



47940. In the digital clock project, the AHDL block codes are connected using graphic design files.



47941. In HDL, one of the strategies used in strategic planning is to find the speed requirements.



47942. In the keypad HDL encoder, the ts bit array represents a tristate buffer.



47943. In the VHDL code of the stepper motor, the cout outputs are bit_vector type because they are binary bit patterns.



47944. In the keypad HDL encoder, as long as all columns are high the ring counter is enabled and counting.



47945. In the frequency counter, the pulse width of the enable signal is very critical for taking an accurate frequency measurement.



47946. One of the first steps in any HDL project is to define its scope by naming each input and output.



47947. The wave-drive sequence of a stepper motor has more torque and operates more smoothly than the full-step sequence at moderate speeds.



47948. In the digital clock project, the ENT input and RCO output can be used for synchronous counter cascading.



47949. In the digital clock project, the 60 Hz signal is sent through a Schmitt-trigger circuit to produce sine wave pulses at the rate of 60 pps.



47950. In the digital clock project HDL, the 1 pps signal is used as a synchronous clock for all of the counters' stages, which are synchronously cascaded.



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