1. Which is not an Altera primitive port identifier?
2. The timing network that sets the output frequency of a 555 astable circuit contains ________.
3. What is the difference between the enable input of the 7475 and the clock input of the 7474?
4. The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is HIGH is called ________.
5. What is another name for a one-shot?
6. On a master-slave flip-flop, when is the master enabled?
7. One example of the use of an S-R flip-flop is as a(n):
8. What is the difference between the 7476 and the 74LS76?
9. Which of the following is correct for a gated D flip-flop?
10. With regard to a D latch, ________.
11. How can the cross-coupled NAND flip-flop be made to have active-HIGH S-R inputs?
12. When is a flip-flop said to be transparent?
13. Four positive edge-triggered D flip-flops are used to store a 4-bit binary number as shown below. Determine if the circuit is functioning properly, and if not, what might be wrong.
14. A 555 operating as a monostable multivibrator has an R1 of 1 M. Determine C1 for a pulse width of 2 s.
15. Master-slave J-K flip-flops are called pulse-triggered or level-triggered devices because input data is read during the entire time the clock pulse is at a LOW level.
16. Which of the following is correct for a D latch?
17. A J-K flip-flop is in a "no change" condition when ________.
18. A correct output is achieved from a master-slave J-K flip-flop only if its inputs are stable while the:
19. Which of the following describes the operation of a positive edge-triggered D flip-flop?
20. What does the triangle on the clock input of a J-K flip-flop mean?
21. A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________.
22. The toggle condition in a master-slave J-K flip-flop means that Q and will switch to their ________ state(s) at the ________.
23. An RC circuit used in a nonretriggerable 74121 one-shot has an REXT of 49 k and a CEXT of 0.2 F. The pulse width (tW) is approximately ________.
24. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________.