digital-electronics-flip-flops Related Question Answers

126. Setup time specifies ________.





127. When the output of the NOR gate S-R flip-flop is Q = 0 and , the inputs are:





128. A retriggerable one-shot has a pulse width of 10 ms; 3 ms after being triggered, another trigger pulse is applied. The resulting output pulse will be ________ mS.





129. Most people would prefer to use ________ over HDL.





130. A major drawback to an latch is its ________.





131. In VHDL, each instance of a component is given a name followed by a ________ and the name of the library primitive.





132. The duty cycle of a 555 timer configured as a basic astable multivibrator is controlled by ________.





133. The major advantage of a Schmitt trigger input is that it ________.





134. When the output of the NOR gate S-R flip-flop is in the HOLD state (no change), the inputs are ________.





135. Regardless of whether you develop a description in AHDL or VHDL, the circuit's proper operation can be verified using a ________.





136. The 74121 nonretriggerable multivibrator can have the output pulse set by a single external component. This component is a(n) ________.





137. The signal used to identify edge-triggered flip-flops is ________.





138. An edge-triggered flip-flop can change states only when ________.





139. When both inputs of a J-K pulse-triggered FF are high and the clock cycles, the output will ________.





140. Plants that are derived from the vegetative organs of a single plant are known as?





141. A gated S-R flip-flop goes into the CLEAR condition when ________.





142. What type of multivibrator is a latch?





143. An astable multivibrator is a circuit that ________.





144. The inputs on a 7474 D flip-flop are S, R, D, and CLK ________ is/are synchronous.





145. An e-mail address typically consists of a user ID followed by the...........sign and the name of the e-mail server that manages the user’s electronic post office box?





146. The asynchronous inputs on a J-K flip-flop ________.





147. A positive edge-triggered flip-flop will accept inputs only when the clock ________.





148. If data is brought into the J terminal and its complement to the K terminal, a J-K flip-flop operates as a(n) ________.





149. The point(s) on this timing diagram where the Q output of a D latch will be HIGH is/are ________.





150. The action of ________ a FF or latch is also called resetting.





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