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digital-electronics-integrated-circuit-logic-families Related Question Answers
1. Which of the following summarizes the important features of ECL?
Good noise immunity, negative logic, high frequency capability, low power dissipation, and short propagation time Low noise margin, low output voltage swing, negative voltage operation, fast, and high power consumption Poor noise immunity, positive supply voltage operation, good low frequency operation, and low power Slow propagation time, high frequency response, low power consumption, and high output voltage swings
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2. What must be done to interface TTL to CMOS?
A 5 V Zener diode must be placed across the inputs of the TTL gates in order to protect them from the higher output voltages of the CMOS gates. A dropping resistor must be used on the CMOS 12 V supply to reduce it to 5 V for the TTL. A pull-up resistor must be used between the TTL output-CMOS input node and Vcc; the value of RP will depend on the number of CMOS gates connected to the node. As long as the CMOS supply voltage is 5 V, they can be interfaced; however, the fan-out of the TTL is limited to five CMOS gates.
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3. What causes low-power Schottky TTL to use less power than the 74XX series TTL?
A larger value resistor Nothing. The 74XX series uses less power. The Schottky-clamped transistor Using NAND gates
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4. What are the major differences between the 5400 and 7400 series of ICs?
The 5400 series are military grade and allow for a wider range of supply voltages and temperatures. The 5400 series are military grade and require tighter supply voltages and temperatures. The 7400 series are an improvement over the original 5400s.
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5. Which of the following statements apply to CMOS devices?
All of the above. All tools, test equipment, and metal workbenches should be tied to earth ground. The devices should be stored and shipped in antistatic tubes or conductive foam. The devices should not be inserted into circuits with the power on.
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6. What must be done to interface CMOS to TTL?
A 5 V Zener diode must be placed across the inputs of the TTL gates in order to protect them from the higher output voltages of the CMOS gates. A dropping resistor must be used on the CMOS 12 V supply to reduce it to 5 V for the TTL. As long as the CMOS supply voltage is 5 V, they can be interfaced; however, the fan-out of the CMOS is limited to two TTL gates. The two series cannot be interfaced without the use of special interface buffers designed for that purpose, such as the open-collector buffers.
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7. What is the static charge that can be stored by your body as you walk across a carpet?
3,000 volts 30,000 volts 300 volts Over 30,000 volts
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8. What type of circuit is shown below, and how is the output ordinarily connected?
Any of the above could be correct, depending on the specific application involved. It is an open-collector gate and is used to drive loads that cannot be connected directly to Vcc due to high noise levels. It is an open-collector gate. An external load must be connected between the output terminal and an appropriate supply voltage. It represents an active-LOW inverter and is used in negative logic systems.
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9. What type of circuit is represented in the given figure, and which statement best describes its operation?
It is a programmable inverter. It can be programmed to function as either an active LOW or an active HIGH inverter. It is a tristate inverter. When the ENABLE input is HIGH, the output is effectively an open circuit—it is neither LOW nor HIGH. It is an active LOW buffer, which can be turned on and off by the ENABLE input. None of the above.
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10. Which of the following logic families has the highest noise margin?
CMOS HCMOS LS TTL TTL
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11. A "floating" TTL input may be defined as:
unused input that is not connected. unused input that is tied to the ground. unused input that is tied to used inputs. unused input that is tied to Vcc through a 1 k resistor.
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12. Which of the logic families listed below allows the highest operating frequency?
54S 74AS ECL HCMOS
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13. Refer to the given figure. What type of output arrangement is being used for the output?
Complementary-symmetry Push-pull Quasi push-pull Totem-pole
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14. Refer the given figure. Which of the following describes the operation of the circuit?
A HIGH input turns Q1, Q2, and Q3 off, and Q4 is on. A HIGH input turns Q1, Q2, and Q4 on; Q3 is off. A LOW input turns Q1 and Q3 on; Q2 and Q4 are off. A LOW input turns Q1 and Q4 off; Q2 and Q3 are on.
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15. What type of logic circuit is shown below and what logic function is being performed?
It is a CMOS AND gate. It is a CMOS NOR gate. It is a PMOS NAND gate. It is an NMOS AND gate.
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16. Whenever a totem-pole TTL output goes from LOW to HIGH, a high-amplitude current spike is drawn from the Vcc supply. How is this effect corrected to a digital circuit?
By connecting a capacitor from Vout to ground By connecting a large resistor from Vcc to Vout By connecting a radio-frequency capacitor from Vcc to ground. By using a switching power supply
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17. What type of circuit is shown below and which statement best describes its operation?
It is a CMOS inverter with tristate output. It is a hybrid TTL-CMOS inverter with FET totem-pole output. It is a two-input CMOS AND gate with open drain. It is a two-input CMOS buffer with tristate output.
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18. What is the increase in switching speed between 74LS series TTL and 74HC/HCT (High-Speed CMOS)?
10 100 5 50
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19. A logic signal experiences a delay in going through a circuit. The two propagation delay times are defined as:
tDLH and tDHL. tHPL and tlph. tLDH and tHDL. tPLH and tPHL.
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20. What does ECL stand for?
It stands for electron-coupled logic; all of the devices used within the gates are N-type transistors. It stands for emitter-coupled logic; all of the emitters of the input transistors are connected together and each transistor functions as an emitter follower. It stands for emitter-coupled logic; all of the inputs are coupled into the device through the emitters of the input transistors. It stands for energy-coupled logic; the input energy is amplified by the input transistors and allows the device to deliver higher output currents.
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21. What is unique about TTL devices such as the 74S00?
The devices use Schottky transistors and diodes to prevent them from going into saturation; this results in faster turn on and turn off times, which translates into higher frequency operation. The gate transistors are silicon (S), and the gates therefore have lower values of leakage current. The S denotes a slow version of the device, which is a consequence of its higher power rating. The S denotes the fact that a single gate is present in the IC rather than the usual package of 2–6 gates.
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22. Refer to the figure given below. What type of device is shown and what input levels are required to turn the LED off?
The device is a Schottky AND gate and requires only one low input to turn the LED off. The device is a Schottky open-collector AND gate and requires a low on both inputs to turn the LED off. The device is an open-collector AND gate and requires both inputs to be HIGH in order to turn the LED off. The device is an open-collector AND gate and requires only one low input to turn the LED off.
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23. Generally, the voltage measured at an unused TTL input would typically be measured between:
0 to 1.8 V. 0 to 5 V. 0.8 to 5 V. 1.4 to 1.8 V.
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24. The IEEE/ANSI notation of an internal underlined diamond denotes:
open-collector outputs. quadrature amplifiers. totem-pole outputs. tristate buffers.
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25. The bipolar TTL logic family that was developed to increase switching speed by preventing transistor saturation is:
current-mode logic (CML). emitter-coupled logic (ECL) and transistor-transistor logic (TTL). emitter-coupled logic (ECL). transistor-transistor logic (TTL).
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