76. It is important to memorize logic symbols, Boolean equations, and truth tables for logic gates.
77. The gates in this figure are implemented using TTL logic. If the input of the inverter is open, and you apply logic pulses to point B, the output of the AND gate will be ________.
78. The gates in this figure are implemented using TTL logic. If the output of the inverter is open, and you apply logic pulses to point B, the output of the AND gate will be ________.
79. If A is LOW or B is LOW or BOTH are LOW, then X is LOW. If A is HIGH and B is HIGH, then X is HIGH. These rules specify the operation of a(n) ________.
80. A major advantage of ECL logic over TTL and CMOS is ________.
81. The output of an XOR gate is HIGH only when ________.
82. A 2-input gate that can be used to pass a digital waveform unchanged at certain times and inverted at other times is a(n) ________.
83. The gates in this figure are implemented using TTL logic. If the output of the inverter has an internal open circuit, what voltage would you expect to measure at the inverter's output?
84. When does the output of a NAND gate = 1?
85. The number of input combinations for a 4-input gate is ________.
86. When does the output of a NOR gate = 0?
87. The output of an AND gate with three inputs, A, B, and C, is HIGH when ________.
88. If a 3-input NOR gate has eight input possibilities, how many of those possibilities will result in a HIGH output?
89. If a signal passing through a gate is inhibited by sending a LOW into one of the inputs, and the output is HIGH, the gate is a(n):
90. A device used to display one or more digital signals so that they can be compared to expected timing diagrams for the signals is a:
91. When used with an IC, what does the term "QUAD" indicate?