electronic-devices-dc-biasing-fets Related Question Answers
26. Which of the following describe(s) the difference(s) between JFETs and depletion-type MOSFETs?
28. Specification sheets typically provide the value of the constant k for enhancement-type MOSFETs.
29. Determine the quiescent values of ID and VGS.
30. In ________ configuration(s) a depletion-type MOSFET can operate in enhancement mode.
31. In a universal JFET bias curve, the horizontal axis is ________.
32. In a fixed-bias configuration, the voltage level of VGS is equal to ________.
33. The ratio of current ID to IDSS is equal to ________ for a fixed-bias configuration.
34. For ________, Shockley's equation is applied to relate the input and the output quantities.
35. The slope of the dc load line in a self-bias configuration is controlled by ________.
36. Specification sheets typically provide ________ for enhancement-type MOSFETs.
37. ‘Shuddhi Movement’ was started by?
38. When plotting the transfer characteristics, choosing VGS = 0.5VP will result in a drain current level of ________ IDSS.
39. The slope of the dc load line in a voltage-divider is controlled by ________.
40. In a feedback-bias configuration, the slope of the dc load line is controlled by ________.
42. In a depletion-type MOSFET, the transfer characteristic rises ________ as VGS becomes more positive.
43. The dc load line is drawn using the equation obtained by applying Kirchhoff's voltage law (KVL) at ________ side loop(s) of the circuit.
44. In a universal JFET bias curve, the vertical scale labeled m is used to find the solution to the ________ configuration.
45. The coupling capacitors are ________ for the dc analysis and ________ for the ac analysis.
46. ________ levels of RS result in ________ quiescent values of ID and ________ negative values of VGS.
47. In an enhancement-type MOSFET, the drain current is zero for levels of VGS less than the ________ level.
48. For the field-effect transistor, the relationship between the input and the output quantities is ________.
49. In p-channel FETs, the level of VGS is ________ while the level of VDS is ________.
50. The controlled variable on the output side of an FET transistor is a ________ level.
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