You Are On Multi Choice Question Bank SET 1022
51101. A JFET data sheet specifies VGS(off) = –10 V and IDSS = 8 mA. Find the value of ID when VGS = –3 V.
51102. Identify the n-channel E-MOSFET.
51103. If VD is less than expected (normal) for a self-biased JFET circuit, then it could be caused by a(n)
51104. ‘Calcutta Chromosome’ is the famous book is written by?
51105. When biased as a variable resistor, JFET resistance (RDS) increases as VGS becomes more negative.
51106. The arrow on the schematic symbol for a MOSFET indicates the channel material type.
51107. A VMOS device can handle higher power and voltage than a conventional MOSFET.
51108. It is not necessary to exercise any particular care in handling a MOSFET.
51109. The Q-point in a JFET with voltage-divider bias is more stable than in a self-biased JFET.
51110. One advantage of a JFET over the BJT is its high input resistance.
51111. An E-MOSFET can be operated with either positive or negative values of VGS.
51112. The MOSFET has no pn junction.
51113. The JFET operates with a reverse-biased pn junction (gate-to source).
51114. The three FET terminals are called source, base, and drain.
51115. The E-MOSFET has no physical channel.
51116. For a JFET, the value of VDS at which ID becomes essentially constant is the
51117. The ________ has a physical channel between the drain and source.
51118. Refer to figure given below. Calculate the value of VDS.
51119. Refer to figure shown below. Determine the value of VS.
51120. A self-biased n-channel JFET has a VD = 6 V. VGS = –3 V. Find the value of VDS.
51121. What is the first phase of the dual-slope method of conversion?
51122. What is the maximum conversion time of a clock rate of 1 MHz operating a 10-stage counter in an ADC?
51123. On which of the following does the conversion depend in ladder-network conversion?
51124. The voltage-controlled oscillator is a subset of the "test bench" function generator.
51125. Which application best describes this 555 timer circuit?
51126. Which of the following applications include a phase-locked loop (PLL) circuit?
51127. Determine the free-running frequency when R3 is set to 2.5 k.
51128. This figure is a block diagram of a(n) ________.
51129. What is the function of a ladder network?
51130. Which of the slope intervals of the integrator does the counter in the analog-to-digital converter (ADC) operate?
51131. A 311 IC is an example of an eight-pin DIP that can be made to function as a ________.
51132. Determine the free-running frequency for this circuit.
51133. What is (are) the level(s) of the input voltage to a ladder-network conversion?
51134. The substance that is least prone to catch and spread fire is?
51135. At which of the following period(s) is the counter advanced (incremented) in dual-slope conversion?
51136. How many Vcc connections does the 565 PLL use?
51137. What is (are) the input(s) to the comparator in the ladder-network conversion of an ADC?
51138. This circuit is an example of a ________.
51139. A collection of cattle is ..........?
51140. How many comparators does a 339 IC contain?
51141. When is the counter set to zero in the dual-slope method of conversion?
51142. The 555 timer IC is made up of a combination of linear comparators and digital flip-flops.
51143. If all plants of the world die, then all the animals will die due to?
51144. Which of the following devices is (are) a component of a digital-to-analog converter (DAC)?
51145. Which of the following circuits is (are) linear/digital ICs?
51146. Which of the following best describes the output of a 566 voltage-controlled oscillator?
51147. What is the voltage resolution of an 8-stage ladder network?
51148. The timing components for a PLL are 15 k and 220 pF. Calculate the free-running frequency.
51149. Which of the following frequencies is associated with the 565 frequency-shift keyed decoder?
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51150. Calculate the frequency of this circuit.
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