48101. The J-K flip-flop is a standard building block of clocked (sequential) logic circuits known as logic standard primitives.
48102. A latch can act as a contact-bounce eliminator.
48103. Connecting components together using HDL is not difficult.
48104. A flip-flop's normal starting state when power is first applied to a circuit is always the SET state.
48105. Latches are tristate devices whose state normally depends on asynchronous inputs.
48106. Using knowledge from previous chapters, an S-R flip-flop circuit is easy to design.
48107. Inputs that cause the output of a flip-flop to change instantaneously are asynchronous.
48108. A one-shot is a special type of multivibrator that must be triggered to produce each output pulse.
48109. Generally, a flip-flop's hold time is short enough so that its output will go to a state determined by the logic levels present at its synchronous control inputs just prior to the active clock transition.
48110. The J-K flip-flop eliminates the invalid state by toggling when both inputs are high and the clock transitions.
48111. A D-type latch is able to change states and "follow" the D input regardless of the level of the ENABLE input.
48112. A positive edge-triggered flip-flop changes states with a HIGH-to-LOW transition on the clock input.
48113. When using edge-triggered flip-flops, the data is entered into the flip-flop on the leading edge of the clock, but the output does not change until the trailing edge of the clock.
48114. A D latch has one data-input line.
48115. The 7474 has two distinct types of inputs: synchronous and asynchronous.
48116. Most basic latches and flip-flops are available in IC packages of eight latches or flip-flops with a common clock.
48117. Edge-triggered flip-flops can be identified by the triangle on the clock input.
48118. Parallel data transfers between two different sets of registers require more than one shift pulse.
48119. A TOGGLE input to a J-K flip-flop causes the Q and outputs to switch to their opposite state.
48120. When the output of the NOR gate S-R flip-flop is and , the inputs are .
48121. Edge-triggered J-K flip-flops make it hard for design engineers to know when to accept input data.
48122. A one-shot circuit is also known as a timer.
48123. The S-R flip-flop has no invalid or unused state.
48124. Pulse-triggered flip-flops are identified by a bubble on the Q output terminal.
48125. Some flip-flops have invalid states.
48126. Multivibrators must be level-triggered.
48127. Simple gate circuits, combinational logic, and transparent S-R flip-flops are synchronous.
48128. A flip-flop is in the CLEAR condition when .
48129. Pulse-triggered or level-triggered devices are the same.
48130. A D flip-flop is constructed by connecting an inverter between the SET and clock terminals.
48131. It takes four flip-flops to act as a divide-by-4 frequency divider.
48132. The gated S-R flip-flop is asynchronous.
48133. The asynchronous inputs are normally labeled ________ and ________, and are normally active-________ inputs.
48134. Assume a J-K flip-flop has 1s on the J and K inputs. The next clock pulse will cause the output to ________.
48135. In synchronous systems, the exact times at which any output can change state are determined by a signal commonly called the ________.
48136. The key to edge-triggered sequential circuits in VHDL is the ________.
48137. Provide meaningful words to fill the blanks: If he came on time, we ......... playing.?
48138. The J-K flip-flop is a standard building block of clocked (sequential) logic circuits known as a ________.
48139. A gated D latch does not have ________.
48140. Setup time specifies ________.
48141. When the output of the NOR gate S-R flip-flop is Q = 0 and , the inputs are:
48142. A retriggerable one-shot has a pulse width of 10 ms; 3 ms after being triggered, another trigger pulse is applied. The resulting output pulse will be ________ mS.
48143. Most people would prefer to use ________ over HDL.
48144. A major drawback to an latch is its ________.
48145. In VHDL, each instance of a component is given a name followed by a ________ and the name of the library primitive.
48146. The duty cycle of a 555 timer configured as a basic astable multivibrator is controlled by ________.
48147. The major advantage of a Schmitt trigger input is that it ________.
48148. When the output of the NOR gate S-R flip-flop is in the HOLD state (no change), the inputs are ________.
48149. Regardless of whether you develop a description in AHDL or VHDL, the circuit's proper operation can be verified using a ________.
48150. The 74121 nonretriggerable multivibrator can have the output pulse set by a single external component. This component is a(n) ________.