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digital-electronics-digital-arithmetic-operations-and-circuits Related Question Answers
51. In VHDL, what is a GENERATE statement?
A way to get the computer to generate a program from a circuit diagram A way to tell the compiler to replicate several components Not used in VHDL or ADHL The start statement of a program
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52. Binary subtraction of a decimal 15 from 43 will utilize which two's complement?
011100 101011 110000 110001
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53. Which of the following is the primary advantage of using binary-coded decimal (BCD) instead of straight binary coding?
BCD codes are easily converted from decimal. BCD codes are easily converted to straight binary codes. Fewer bits are required to represent a decimal number with the BCD code. the relative ease of converting to and from decimal
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54. Convert each of the decimal numbers to two's-complement form and perform the addition in binary.
+13 –10 add –7 add +15
0000 0110 0000 0101 0000 0110 0001 1001 0001 0100 0000 0101 1111 0110 1111 0101
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55. Add the following binary numbers.
0010 0110   0011 1011   0011 1100 +0101 0101   +0001 1110   +0001 1111
0111 0111 0100 0001 0101 1011 0111 0111 0101 1001 0101 1011 0111 1011 0100 0001 0101 1011 0111 1011 0101 1001 0101 1011
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56. The carry propagation delay in full-adder circuits:
decreases in a direct ratio to the total number of FA stages. increases in a direct ratio to the total number of FA stages but is not a factor in limiting the speed of arithmetic operations. is cumulative for each stage and limits the speed at which arithmetic operations are performed. is normally not a consideration because the delays are usually in the nanosecond range.
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57. What is the difference between a full-adder and a half-adder?
Full-adder does not have a carry-out. Full-adder has a carry-in. Half-adder does not have a carry-out. Half-adder has a carry-in.
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58. The summing outputs of a half- or full-adder are designated by which Greek symbol?
lambda omega sigma theta
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59. Subtract the following hexadecimal numbers.
47   34   FA –25   –1C   –2F
22 17 CB 22 18 CB 22 18 CC 22 19 CB
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60. What is the correct output of the adder in the given figure, with the outputs in the order:
01101 10011 10111 11101
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61. The BCD addition of 910 and 710 will give initial code groups of 1001 + 0111. Addition of these groups generates a carry to the next higher position. The correct solution to this problem would be to:
add 0110 to both code groups to validate the carry from the lowest order code group add 0110 to the lowest order code group because a carry was generated and then prefix the carry with three zeros disregard the carry and add 0110 to the lowest order code group ignore the lowest order code group because 0000 is a valid code group and prefix the carry with three zeros
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62. Subtract the following binary numbers.
0101 1000   1010 0011   1101 1110 –0010 0011   –0011 1000   –0101 0111
0011 0100 0110 1010 1000 0110 0011 0101 0110 1010 1000 0110 0011 0101 0110 1010 1000 0111 0011 0101 0110 1011 1000 0111
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63. Why is a fast-look-ahead carry circuit used in the 7483 4-bit full-adder?
to decrease the cost to make it smaller to slow down the circuit to speed up the circuit
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65. What logic function is the sum output of a half-adder?
AND exclusive-NOR exclusive-OR NAND
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66. The binary adder circuit is designed to add ________ binary numbers at the same time.
2 4 6 8
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67. An ALU is a multipurpose device capable of providing several different logic operations.
False True
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73. Overflow indicators in ALU circuits indicate when add or subtract operations produce results that are too large to fit into four bits.
False True
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75. Larger number capacities may be obtained from 2-bit adders by paralleling them.
False True
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