76. The timing and control block provides the ________ for the frequency counter.
77. The stepper motor HDL will ignore its counter inputs and pass control inputs directly to the output when set in mode ________.
78. The full-step sequence of a stepper motor always has two coils energized in any state of the sequence and typically causes ________ of shaft rotation per step.
79. Depending on the ________ the IC is in, the output of the stepper motor HDL will respond to each pulse by changing state.
80. The step rate of the simulation of a stepper motor is probably ________ the actual stepper motor.
81. A very critical dimension in project management is ________.
82. In the digital clock design, the hours section is different from the seconds and minutes section in that it never goes to ________.
83. In the digital clock project, a 60 pps input is transformed into a 1 pps timing signal. The block is called ________.
84. In the stepper motor, the half-step sequence is used when ________.
85. In the keypad encoder, the ________ detects when a key is pressed.
86. In a frequency counter, what happens at high frequencies when the sampling interval is too long?
87. In the digital clock project, when does the PM indicator go high?
88. How is the output frequency related to the sampling interval of a frequency counter?
89. In an HDL application of a stepper motor, after an up/down counter is built what is done next?
90. In a digital clock application, the basic frequency must be divided down to: