1. In the keypad application, what does the data signal define?
2. What does the ring counter in the HDL keypad application do when a key is pressed?
3. In the digital clock project, the purpose of the frequency prescaler is to:
4. Which is not a step that should be followed in project management?
5. In the keypad application, what does the preset state of the ring counter define?
6. In an HDL stepper motor design, why is there more than one mode?
7. Which is not a major block of an HDL frequency counter?
8. In a full-step sequence involving two flip-flops driving four coils of a stepper motor, how far will the stepper motor step?
9. Which is not a step used to define the scope of an HDL project?
10. In the digital clock project, what is the frequency of the MOD-6 counter in the minutes section?
11. Why should a real hardware functional test be performed on the HDL stepper motor design?
12. What does the major block of an HDL code emulation of a keypad include?
13. The accuracy of the frequency counter depends on the:
14. In the frequency counter, if the clock generator produces a 100 kHz system clock signal, how many decade counters are required to measure 1 Hz?
15. What must a stepper motor HDL application include?
16. Which is not a step in strategic planning for HDL development?
17. In the frequency counter, when is the new count stored in the display register?
18. What are two ways to remember the current state of a counter in VHDL?
19. In the digital clock project, what type of counter is used to count to 59 seconds?
20. In the keypad application, when all columns are HIGH, the ring counter is enabled and counting, and dav is LOW, what is the status of the d outputs?
21. In the frequency counter, what is the function of the Schmitt trigger circuit?
22. List three basic blocks in the digital clock project.
23. When designing an HDL digital system, which is the worst mistake one can make?
24. In the keypad application, just after the 4 ms mark the simulation imitates the release of the key by changing the column value back to F hex, which causes the d output to go into its Hi-Z state. On the next rising clock edge, what happens to dav?
25. For the frequency counter, which is not a control signal from the control and timing block?