51. In the digital clock project, when it is 11:59:59, AND gate 1 detects that the tens of hours is 1 and the edge trigger clock moves the display to 12:00:00.
52. In the keypad HDL encoder, after releasing a key the ring counter resumes its counting sequence.
53. In the keypad HDL encoder, the freeze bit detects when a key is released.
54. In HDL when a circuit is simulated on a computer, the designer must create all the different scenarios that will be experienced by the actual circuit and must also know the proper response to those inputs.
55. In the keypad HDL encoder, NANDing of the columns is used to activate the freeze bit.
56. In the digital clock project, the 1 pps signal is used as a synchronous clock for all of the counter stages, which are ________.
57. In the keypad encoder, the ________ must hold in its current state until a key is released.
58. The interface of the stepper motor needs to operate in one of ________ mode(s).
59. In the digital clock project, the 60 Hz signal is sent through a Schmitt-trigger circuit to produce square pulses at the rate of ________.
60. A frequency counter ________ a signal.
61. When coming up with a strategy for dividing the overall project into manageable-size pieces one must ________.
62. VARIABLES are considered to be updated ________ within a sequence of statements in a PROCESS, whereas SIGNALS referred to in a PROCESS are updated when the PROCESS ________.
63. The major blocks of the frequency counter are the counter, ________, decoder/display, and the timing and control unit.
64. In the keypad encoder, just after the 4 ms mark, the simulation initiates the release of the key by changing the column value to ________, which causes the d output to go into its Hi-Z state.
65. One aspect of project planning and management is the selection of ________ that will best fit the application.
66. In the keypad encoder, the ring counter is implemented using ________ that responds to the clk input.
67. In the digital clock project, when it is 11:59:59, AND gate 1 detects that the tens of hours is 1 and the enable input is active. On the next clock pulse the AM/PM flip-flop will ________.
68. In the frequency counter, the control clock is derived from the ________ by frequency dividers controlled in the control and timing block.
69. Using one case construct inside another is known as ________.
70. In the frequency counter, the length of time for the ________ to be enabled can be selected with the range select input.
71. In the digital clock project HDL code, the MOD-12 counter is using ________.
72. Each ________, starting at the simplest level, should be built in HDL.
73. In the keypad encoder, the ________ activate(s) the freeze bit only when one column is low.
74. In a real project, the first step of definition often involves some ________ on the part of the project manager.
75. One of the first steps in small-project management is to determine ________.