26. A bidirectional 4-bit shift register is storing the nibble 1110. Its input is LOW. The nibble 0111 is waiting to be entered on the serial data-input line. After two clock pulses, the shift register is storing ________.
27. In a parallel in/parallel out shift register, D0 = 1, D1 = 1, D2 = 1, and D3 = 0. After three clock pulses, the data outputs are ________.
28. The group of bits 10110111 is serially shifted (right-most bit first) into an 8-bit parallel output shift register with an initial state 11110000. After two clock pulses, the register contains ________.
29. By adding recirculating lines to a 4-bit parallel-in, serial-out shift register, it becomes a ________, ________, and ________-out register.
30. What type of register would have a complete binary number shifted in one bit at a time and have all the stored bits shifted out one at a time?
31. When an 8-bit serial in/serial out shift register is used for a 20 s time delay, the clock frequency is ________.
32. Ring shift and Johnson counters are:
33. What is the difference between a shift-right register and a shift-left register?
34. What is a transceiver circuit?
35. A 74HC195 4-bit parallel access shift register can be used for ________.
36. Which type of device may be used to interface a parallel data format with external equipment's serial format?
37. What is the function of a buffer circuit?
38. What is the preset condition for a ring shift counter?
39. Which is not characteristic of a shift register?
40. To keep output data accurate, 4-bit series-in, parallel-out shift registers employ a ________.
41. With a 50 kHz clock frequency, six bits can be serially entered into a shift register in ________.
42. Another way to connect devices to a shared data bus is to use a ________.
43. To serially shift a nibble (four bits) of data into a shift register, there must be ________.
44. Computers operate on data internally in a ________ format.
45. In a 4-bit Johnson counter sequence there are a total of how many states, or bit patterns?
46. If a 10-bit ring counter has an initial state 1101000000, what is the state after the second clock pulse?
47. How much storage capacity does each stage in a shift register represent?
48. When the output of a tristate shift register is disabled, the output level is placed in a:
49. One of the stages in a register consists of a latch.
50. There are several ways to construct a stepper motor to achieve digitally controlled stepping action. One possibility is to construct four stator coils set up as four pole pairs, each 45° apart and using three ferromagnetic pairs spaced 60° apart.