51. A parallel load operation is asynchronous, so it is not dependent on the clock.
52. A ferromagnetic material is one that forms a resistance to magnetic fields.
53. A counter has a specified sequence of states, but a shift register does not.
54. In a 74164 8-bit shift register, in order for the parallel data output to be synchronously loaded on the negative clock edge, the parallel enable input is LOW.
55. Practically every possible load, shift, and conversion operation is available in a shift register IC.
56. Using separate serial inputs for shifting left or shifting right is a major difference between the 74194 and other shift registers.
57. Parallel load means to load all flip-flops at the same time.
58. The ring and Johnson shift counters are uncommon circuits that are similar to synchronous counters.
59. A stepper motor makes its rotation in smooth continuous motion.
60. A universal shift register has both serial and parallel input and output capacity.
61. The storage capacity of a register makes it an important type of memory.
62. The 74194 4-bit bidirectional universal shift register has a wide range of applications.
63. To transmit parallel data over a serial cable, the data must first go through data conversion to the serial format.
64. A ring counter is a register in which a certain pattern of 1s and 0s is continuously outputted in parallel.
65. Bidirectional means having two states.
66. Eight states are in an 8-bit Johnson counter sequence.
67. A stage is two storage elements in a register.
68. When is LOW, the data are shifted one bit per clock pulse.
69. Assume a LOW logic level is placed on the SHIFT/LOAD input of a 74195 shift register. The output will change ________.
70. A type of shift register in which the Q or Q output of one stage is not connected to the input of the next stage is ________.
71. A Johnson counter, constructed with N flip-flops, has how many unique states?
72. A type of shift register that requires access to the Q outputs of all stages is ________.
73. An 8-bit serial in/parallel out shift register is clocked at 4 MHz and is used to delay a serial digital signal by 1.25 s. The output that has the proper delay is ________.
74. A 4-bit ring counter is loaded with a single 1. The frequency of any given output is ________.
75. Shifting a binary number to the left by one position is equivalent to ________.