1. When the output of a tri-state shift register is disabled, the output level is placed in a:
2. A comparison between ring and johnson counters indicates that:
3. What is meant by parallel-loading the register?
4. What is a shift register that will accept a parallel input and can shift data left or right called?
5. What happens to the parallel output word in an asynchronous binary down counter whenever a clock pulse occurs?
6. Mod-6 and mod-12 counters are most commonly used in:
7. The serial-in, parallel-out shift register transfers data from one parallel data bus to another parallel data bus one bit at a time across a single line.
8. A serial-in, serial-out shift register transfers data from one line of a parallel bus to another line one bit at a time.
9. Counters are common components in digital clocks.
10. In an asynchronous counter, each state is clocked by the same pulse.
11. A multiplexed display circuit uses a technique called time division modulation.
12. An asynchronous decade counter increases its value by ten for each clock pulse.
13. A parallel-in, serial-out shift register enters all data bits simultaneously and transfers them out one bit at a time.
14. The modulus (mod) of a counter is the same as its maximum count (N).
15. Synchronous construction reduces the delay time of a counter to the delay of __________.
16. A 4-bit PISO shift register that receives 4 bits of parallel data will shift to the ________ by ________ position(s) for each clock pulse.
17. To operate correctly, starting a ring counter requires __________.
18. A sequence of equally spaced timing pulses may be easily generated by a(n) __________.
19. A _________ shift register can shift stored data either left or right.
20. Ring and johnson counters are _______.
21. When two counters are cascaded, the overall mod number is equal to the __________ of their individual mod numbers.
22. What type of register would shift a complete binary number in one bit at a time and shift all the stored bits out one bit at a time?
23. Synchronous counters eliminate the delay problems encountered with asynchronous (ripple) counters because the:
24. One of the major drawbacks to the use of asynchronous counters is that: