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You Are On Multi Choice Question Bank SET 1144

57201. For the logic circuit of the given figure the simplified Boolean equation

57202. A combination circuit is one in which the output depends on

57203. 718 = __________ .

57204. Boolean expression for the output of XNOR (Equivalent) logic gate with inputs A and B is

57205. An SR flip flop can be built using NOR gates or NAND gates.

57206. In the given figure RC = RL = 1 kΩ, then V0 =

57207. A 14 pin NOT gate 1C has __________ NOT gates.

57208. F's complement of (2BFD)hex is

57209. Assertion (A): Master slave JK flip flop is commonly used in high speed synchronous circuitry Reason (R): Master slave JK flip flop uses two JK flip flops in cascade.

57210. Inputs A and B of the given figure are applied to a NAND gate. The output is LOW

57211. ECL is a saturating logic.

57212. For the NMOS gate in the given figure, F =

57213. The resolution of 4 bit counting ADC is 0.5 volt, for an Analog input of 6.6 volts. The digital output of ADC will be

57214. 9's complement of 1210 is

57215. The minterm designation for ABCD is

57216. Read the following statements The circuitry of ripple counter is more complex than that of synchronous counter.The maximum frequency of operation of ripple counter depends on the modulus of the counter.The maximum frequency of operation of synchronous counter does not depend on the modulus of the counter. Which of the above statements are correct?

57217. The role of the payment gateway is

57218. A multiple emitter transistor has many emitters and collectors.

57219. A mode-10 counter can divide the clock frequency by a factor of

57220. Which of the following binary numbers is equivalent to decimal 10?

57221. A 4 bit synchronous counter has flip flops having propagation delay of 50 ns each and AND gates having propagation delay of 20 ns each. The maximum frequency of clock pulses can be

57222. A counter has 4 flip flops. It divides the input frequency by

57223. A pulse train with a 1 MHz frequency is counted using a 1024 modulus ripple counter using JK flip flops. The maximum propagation delay for each flip-flop should be

57224. What will be maximum input that can be converted for a 6 bit dual slope A/D converter uses a reference of -6v and a 1 MHz clock. It uses a fixed count of 40 (101000).

57225. In the given figure shows a logic circuit. The minimum Boolean expression for this circuit is

57226. If number of information bits is 11, the number of parity bits in Hamming code is

57227. The number of digit 1 present in the binary representation of 3 x 512 + 7 x 64 + 5 x 8 + 3 is

57228. Out of 5 M x 8, 1 M x 16, 2 M x 16 and 3M x 8 memories, which memory can store more bits?

57229. A 6 bit ladder A/D converter has input 101001. The output is (assume 0 = 0 V and 1 = 10 V)

57230. A ripple counter has 4 bits and uses flip flops with propagation delay time of 25 ns. The maximum possible time for change of state will be

57231. A counter has a modulus of 10. The number of flip flops is

57232. The counter shown in the given figure is built using 4 -ve edge triggered toggle FFs. The FF can be set asynchronously when R = 0. The combinational logic required to realize a modulo-13 counter is

57233. In the figure, the LED

57234. A 4 bit ripple counter uses flip flops with propagation delay of 50 ns each. The maximum clock frequency which can be used is

57235. An AND gate has two inputs A and B and one inhibit input S. Out of total 8 input states, output is 1 in

57236. 26810 = __________ .

57237. In a JK Master slave flip flop

57238. The counter which require maximum number of FF for a given mod counter is

57239. Four inputs A, B, C, D are fed to a NOR gate. The output of NOR gate is fed to an inverter. The output of inverter is

57240. The content of which of the following determines the state of the CPU at the end of the execute cycle (when the interrupt is recognized)? Program counterProcessor registerCertain status conditions Select the correct answer using the codes given below :

57241. In a gate output is Low if and only if all inputs are High. The gate is

57242. With on-chip decoding, n address lines can access

57243. The circuit in the figure is has two CMOS-NOR gates. This circuit functions as a

57244. A 6 bit DAC uses binary weighted resistors. If MSB resistor is 20 k ohm, the value of LSB resistor is

57245. A 6 bit dual slope A/D converter uses a reference of -6v and a 1 MHz clock. It uses a fixed count of 40 (101000). Then, what will be input, if the output register shows 100111 at the end of conversion.

57246. In the TTL circuit in the figure, S2 to S0 are select lines and X7 to X0 are input lines. S0 and X0 are LSBs. The output Y is

57247. The number of accumulators in 6800 are

57248. If an analog voltage is expressed in binary using 4 bits, each successive binary count would represent

57249. In a 4 input AND gate, the total number of High outputs for 16 input states are

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