3. How many product terms can a MAX+Plus II compiler borrow from adjacent macrocells in the same LAB?
4. Each programmable array logic (PAL) gate product is applied to an OR gate and, if combinational logic is desired, the product is ORed and then:
5. ________ are used at the inputs of PAL/GAL devices in order to prevent input loading from a large number of AND gates.
6. A(n) ________ consists of a programmable array of AND gates that connects to a fixed array of OR gates and is usually OTP.
7. What is another name for digital circuitry called sequential logic?
8. When did the first PLD appear?
9. SPLDs, CPLDs, and FPGAs are all which type of device?
10. Cascade chains are closely associated with ________.
11. FPLA is:
12. A(n) ________ is a section of embedded logic that is commonly found in FPGAs.
13. In a FLEX10K, what two outputs will the LE produce?
14. What is the major downfall of microprocessor/DSP systems?
15. ASIC stands for:
16. A look-up table is simply a truth table with all the possible output connections listed with their desired input response.
17. The final step in the device programming sequence is ________.
18. Most look-up tables in field-programmable gate arrays (FGPAs) use ________ inputs, resulting in ________ possible outputs.
19. What is the defining difference between microprocessor/DSP systems and other digital systems?
20. Why have PLDs taken over so much of the market?
21. CLB is the acronym for ________.
22. What can the GAL22V10 do that the GAL16V8 cannot?
23. Bird: Cage (Select the pair that best expresses similar relationship)?
24. A circuit that implements a combinational logic function by storing a list of output values that correspond to all possible input combinations is a(n) ________.
25. By adding an OR gate to a simple programmable logic device (SPLD) the foundation for a(n) ________ is made possible.