101. In the FLEX10K device, the LE can produce two outputs to drive local (LAB) and global (fast track) interconnects on the chip.
102. The architecture of a PAL differs slightly from that of a PROM.
103. LUT is an acronym for look-up table.
104. A PAL uses a programmable OR array followed by a fixed AND array.
105. The SRAM technology is volatile.
106. The major structures of the MAX7000S are the logic array block (LAB) and the programmable intermediate array (PIA).
107. All I/O pins in the MAX7000S family have a tristate buffer.
108. Based on the high-density architecture of logic cells, FLEX10K devices are generally classified as HCPLDs.
109. A CPLD is basically a simplified PLD.
110. The GAL22V10 has 12 outputs pins and 10 input pins.
111. The GAL16V8 has 32 input variables.
112. Xilinx software uses triangular symbols called buffers to define pins as input or output.
113. A unit of logic in an FPGA that is made up of multiple smaller logic modules and a local programmer interconnect that is used to connect internal logic modules is called a ________.
114. In a FLEX10K device, the carry chain provides a fast carry forward function between ________.
115. The Boolean expression (A + B)(C + D) is an example of ________.
116. An Altera FLEX10K device uses a(n) ________ architecture.
117. The ________ is the most popular standard logic device family today.
118. A GAL22V10 ________.
119. Most FPGA logic modules utilize a(n) ________ approach to create the desired logic functions.
120. An EPM 7128S in a ________ PQFP package has 12 I/O per LAB plus 4 additional input-only pins for a total of 100 pins.
121. A macrocell is ________.
122. The final step in a design flow in which the logic design is implemented in the target device is called ________.
123. In the GAL16V8, the ________ controls the tristate buffer's enable input.
124. All inputs to the MAX7000S device and all macrocell outputs feed the ________.
125. In the GAL16V8, the ________ selects the signal that is fed back into the input matrix.